PCI1520-EP Datasheet, PDF (27/138 Pages) Texas Instruments – PC Card Controllers

TERMINAL
NO.
NAME
PDV GHK
AD31 171 E12
AD30 172 C12
AD29 175 A11
AD28 176 B11
AD27 178 E11
AD26 179 F11
AD25 167 F12
AD24 181 B10
AD23 184 F10
AD22 186 B09
AD21 187 C09
AD20 188 F09
AD19 189 E09
AD18 190 A08
AD17 191 B08
AD16 192 C08
AD15 205 B05
AD14 206 E06
AD13 207 C05
AD12 208 A04
AD11 173 B12
AD10
1
D01
AD9
2
E03
AD8
3
F05
AD7
5
E02
AD6
7
F03
AD5
8
F02
AD4
9 G05
AD3
10 F01
AD2
11 H06
AD1
12 G03
AD0
13 G02
C/BE3 164 B14
C/BE2 193 F08
C/BE1 204 F06
C/BE0 4 G06
PAR 203 A05
Table 2−8. PCI Address and Data Terminals
I/O
DESCRIPTION
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
I/O interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a 32-bit address or
other destination information. During the data phase, AD31−AD0 contain data.
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary-bus PCI cycle, C/BE3−C/BE0 define the bus command. During the data
I/O phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit
data bus carry meaningful data. C/BE0 applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8),
C/BE2 applies to byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).
PCI-bus parity. In all PCI-bus read and write cycles, the PCI1520 calculates even parity across the
I/O
AD31−AD0 and C/BE3−C/BE0 buses. As an initiator during PCI cycles, the PCI1520 outputs this parity
indicator with a one-PCLK delay. As a target during PCI cycles, the PCI1520 compares its calculated parity
to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR).
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