TM4C123BH6PM Datasheet, PDF (5/1277 Pages) Texas Instruments – Tiva TM4C123BH6PM Microcontroller

Tiva^™ TM4C123BH6PM Microcontroller
5.2.6
5.3
5.4
5.5
5.6
System Control ........................................................................................................... 221
Initialization and Configuration ..................................................................................... 225
Register Map .............................................................................................................. 226
System Control Register Descriptions ........................................................................... 231
System Control Legacy Register Descriptions ............................................................... 412
6
System Exception Module ................................................................................... 473
6.1 Functional Description ................................................................................................. 473
6.2 Register Map .............................................................................................................. 473
6.3 Register Descriptions .................................................................................................. 473
7
Hibernation Module .............................................................................................. 481
7.1 Block Diagram ............................................................................................................ 482
7.2 Signal Description ....................................................................................................... 482
7.3 Functional Description ................................................................................................. 483
7.3.1 Register Access Timing ............................................................................................... 483
7.3.2 Hibernation Clock Source ............................................................................................ 484
7.3.3 System Implementation ............................................................................................... 485
7.3.4 Battery Management ................................................................................................... 486
7.3.5 Real-Time Clock .......................................................................................................... 487
7.3.6 Battery-Backed Memory .............................................................................................. 489
7.3.7 Power Control Using HIB ............................................................................................. 489
7.3.8 Power Control Using VDD3ON Mode ........................................................................... 489
7.3.9 Initiating Hibernate ...................................................................................................... 489
7.3.10 Waking from Hibernate ................................................................................................ 489
7.3.11 Arbitrary Power Removal ............................................................................................. 490
7.3.12 Interrupts and Status ................................................................................................... 490
7.4 Initialization and Configuration ..................................................................................... 491
7.4.1 Initialization ................................................................................................................. 491
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 492
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 492
7.4.4 External Wake-Up from Hibernation .............................................................................. 492
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 493
7.5 Register Map .............................................................................................................. 493
7.6 Register Descriptions .................................................................................................. 494
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.4
8.5
8.6
Internal Memory ................................................................................................... 512
Block Diagram ............................................................................................................ 512
Functional Description ................................................................................................. 513
SRAM ........................................................................................................................ 513
ROM .......................................................................................................................... 514
Flash Memory ............................................................................................................. 516
EEPROM .................................................................................................................... 522
Register Map .............................................................................................................. 528
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 529
EEPROM Register Descriptions (EEPROM Offset) ........................................................ 547
Memory Register Descriptions (System Control Offset) .................................................. 564
9
Micro Direct Memory Access (μDMA) ................................................................ 573
9.1 Block Diagram ............................................................................................................ 574
9.2 Functional Description ................................................................................................. 574
June 12, 2014
5
Texas Instruments-Production Data