TM4C123BH6PM Datasheet, PDF (1246/1277 Pages) Texas Instruments – Tiva TM4C123BH6PM Microcontroller

Electrical Characteristics
Table 23-18. Main Oscillator Input Characteristics (continued)
Parameter Parameter Name
Min
Nom
Max
Unit
V_IL
V_HYS
CMOS input low level, when using an external oscillator
CMOS input buffer hysteresis, when using an external
oscillator
GND
150
-
0.35 * V_DD
V
-
-
mV
DC_{OSC_EXT} External clock reference duty cycle
45
-
55
%
a. 5 MHz is the minimum when using the PLL.
b. See information below table.
c. Crystal ESR specified by crystal manufacturer.
d. Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors
generic crystal datasheet show limits outside of these specifications.
e. OSC_PWR = (2 * pi * F_P * C_L * 2.5)² * ESR / 2. An estimation of the typical power delivered to the crystal is based on the
C_L, F_P and ESR parameters of the crystal in the circuit as calculated by the OSC_PWR equation. Ensure that the value
calculated for OSC_PWR does not exceed the crystal's drive-level maximum.
f. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
The load capacitors added on the board, C₁ and C₂, should be chosen such that the following
equation is satisfied (see Table 23-18 on page 1245 for typical values and Table 23-19 on page 1247
for detailed crystal parameter information).
■ C_L = load capacitance specified by crystal manufacturer
■ C_L = (C₁*C₂)/(C₁+C₂) + C_SHUNT
■ C_SHUNT = C₀ + C_PKG + C_PCB (total shunt capacitance seen across OSC0, OSC1 crystal inputs)
■ C_PKG, C_PCB = the mutual caps as measured across the OSC0,OSC1 pins excluding the crystal.
■ C₀ = Shunt capacitance of crystal specified by the crystal manufacturer
Table 23-19 on page 1247 lists part numbers of crystals that have been simulated and confirmed to
operate within the specifications in Table 23-18 on page 1245. Other crystals that have nearly identical
crystal parameters can be expected to work as well.
In the table below, the crystal parameters labeled C0, C1 and L1 are values that are obtained from
the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals
on a network analyzer. The parameters labeled ESR, DL and C_L are maximum numbers usually
available in the data sheet for a crystal.
The table also includes three columns of Recommended Component Values. These values apply
to system board components. C₁ and C₂ are the values in pico Farads of the load capacitors that
should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. Rs is the
value in kΩ of a resistor that is placed in series with the crystal between the OSC1 pin and the crystal
pin. Rs dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use
the recommended C₁, C₂, and Rs values with the associated crystal part. The values in the table
were used in the simulation to ensure crystal startup and to determine the worst case drive level
(WC Dl). The value in the WC Dl column should not be greater than the Max Dl Crystal parameter.
The WC Dl value can be used to determine if a crystal with similar parameter values but a lower
Max Dl value is acceptable.
1246
Texas Instruments-Production Data
June 12, 2014