OPA322-Q1 Datasheet, PDF (5/26 Pages) Texas Instruments – CMOS Operational Amplifier With Shutdown

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OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: V_S = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V (continued)
Boldface limits apply over the specified temperature range, T_A = –40°C to 125°C.
At T_A = 25°C, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, V_OUT = V_S / 2, and SHDN_x = V_S+, unless otherwise noted.
PARAMETER
TEST CONDITIONS
OPA322-Q1, OPA322S-Q1, OPA2322-Q1,
OPA2322S-Q1, OPA4322-Q1, OPA4322S-Q1
UNIT
MIN
TYP
MAX
OUTPUT
Voltage output swing from
both rails
V_O
R_L = 10 kΩ
10
30
mV
Over temperature
Short-circuit current
Capacitive load drive
Open-loop output resistance
POWER SUPPLY
R_L = 10 kΩ
I_SC
V_S = 5.5 V
C_L
R_O
I_O = 0 mA, f = 1 MHz
40
mV
±65
mA
See Typical Characteristics
90
Ω
Specified voltage range
Quiescent current per amplifier
OPA322-Q1, OPA322S-Q1
Over temperature
OPA2322-Q1, OPA2322S-Q1
Over temperature
OPA4322-Q1, OPA4322S-Q1
Over temperature
Power-on time
SHUTDOWN ⁽²⁾
Quiescent current, per amplifier
High voltage (enabled)
Low voltage (disabled)
Amplifier enable time (full
shutdown) ⁽³⁾
V_S
I_Q
I_O = 0 mA, V_S = 5.5 V
I_O = 0 mA, V_S = 5.5 V
I_O = 0 mA, V_S = 5.5 V
I_O = 0 mA, V_S = 5.5 V
I_O = 0 mA, V_S = 5.5 V
I_O = 0 mA, V_S = 5.5 V
I_O = 0 mA, V_S = 5.5 V
V_S+ = 0 V to 5 V, to 90% I_Q level
V_S = 1.8 V to 5.5 V
I_QSD
All amplifiers disabled, SHDN = V_S–
V_IH
Amplifier enabled
V_IL
Amplifier disabled
1.8
5.5
V
1.6
1.9
mA
2
mA
1.5
1.75
mA
1.85
mA
1.4
1.65
mA
1.75
mA
28
μs
0.1
0.5
µA
(V+) - 0.1
V
(V–) + 0.1
V
t_ON Full shutdown; G = 1, V_OUT = 0.9 × V_S / 2 ⁽⁴⁾
10
µs
Amplifier enable time (partial
shutdown) ⁽³⁾
t_ON Partial shutdown; G = 1, V_OUT = 0.9 × V_S / 2 ⁽⁴⁾
6
µs
Amplifier disable time⁽³⁾
t_OFF
G = 1, V_OUT = 0.1 × V_S / 2
3
µs
SHDN pin input bias current (per pin)
V_IH = 5 V
V_IL = 0 V
0.13
µA
0.04
µA
TEMPERATURE
Specified range
–40
125
°C
Operating range
–40
150
°C
(2) Ensured by design and characterization; not production tested.
(3) The definition of isable time (t_OFF) and enable time (t_ON) is the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual OPA2322S-Q1 having both channels A and B disabled (SHDN_A = SHDN_B = V_S–) and the quad
OPA4322S-Q1 having all channels A to D disabled (SHDN_A/B = SHDN_C/D = V_S–). Partial shutdown exercises only one SHDN pin; in
this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
Copyright © 2013, Texas Instruments Incorporated
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