OPA322-Q1 Datasheet, PDF (12/26 Pages) Texas Instruments – CMOS Operational Amplifier With Shutdown

OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
APPLICATION INFORMATION
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OPERATING VOLTAGE
The OPA322-Q1 family of operational amplifiers are unity-gain stable and can operate on a single-supply voltage
(1.8 V to 5.5 V), or a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The
power-supply pins should have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). The specifications
of these amplifiers fully apply from 1.8 V to 5.5 V and over the extended temperature range of –40°C to 125°C.
Parameters that can exhibit variance with regard to operating voltage or temperature are presented in the Typical
Characteristics.
INPUT AND ESD PROTECTION
The OPA322-Q1 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as
the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Many input signals are
inherently current-limited to less than 10 mA; therefore, there is no need for a limiting resistor. Figure 30 shows
how one may add a series input resistor (R_S) to the driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input; keep the value minimal in noise-sensitive applications.
I_OVERLOAD
10 mA, Max
V_IN
R_S
V+
OPA322-Q1
V_OUT
Figure 30. Input Current Protection
PHASE REVERSAL
The design of the OPA322-Q1 operational amplifiers is for immunity to phase reversal when the input pins
exceed the supply voltages, therefore providing further in-system stability and predictability. Figure 31 shows the
input voltage exceeding the supply voltage without any phase reversal.
4
V_S = ±2.5 V
V_IN
3
2
V_OUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
Time (ms)
750 1000
Figure 31. No Phase Reversal
12
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