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LP8755_14 Datasheet, PDF (5/51 Pages) Texas Instruments – Multi-Phase 6-Core Step-Down Converter
LP8755
www.ti.com
SNVSA20 – NOVEMBER 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)(2)
INPUT VOLTAGE
Voltage on Power Connections (VIOSYS, VDDA5V, VINBxx)
Voltage on Logic Pins (Input or Output Pins) (SCLSYS, SDASYS, NRST, NSLP, ADDR,
INT, SCLSR, SDASR)
Buck switch nodes (SWBxx)
VLDO, FBB0+/B0, FBB0−/B1, FBB2, FBB3+/B3, FBB3−/B4, FBB5
All other analog pins
TEMPERATURE
Junction Temperature (TJ-MAX)
Storage Temperature Range
Maximum Lead Temperature (Soldering, 10 sec.)(3)
ESD RATING(4)
All Pins
Human Body Model
Charge Device Model
−0.3V to +6.0V
−0.3V to +6.0V
(GND-0.2V) to (VINBxx + 0.2V) with +6.0V
max
−0.3V to +2.0V
−0.3V to +6.0V
+150°C
−65°C to +150° C
260°C
1 kV
250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If
Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) All voltage values are with respect to network ground terminal.
(3) For detailed soldering specifications and information, please refer to Application Note 1112: DSBGA Wafer Level chip Scale Package
(AN-1112)
(4) The Human Body Model applicable standard JESD22–A114C, and Charge Device Model applicable standard JESD22–C101.
THERMAL INFORMATION
THERMAL METRIC(1)
LP8755
YFQ
UNITS
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
49 PINS
49.2
0.2
6.6
2.9
6.5
n/a
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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