LP8755_14 Datasheet, PDF (32/51 Pages) Texas Instruments – Multi-Phase 6-Core Step-Down Converter

LP8755
SNVSA20 – NOVEMBER 2013
Inductor Current Dropping to Zero in ~2 µs (All
Converters, All Phases)
HW RST by NRST
OTP_MEM_READ
SW RST by I2C
tRST1
www.ti.com
tRST2
tRST2
0
~2 2s
Time
Figure 43. Fast Power-Down Sequence
OTP_MEM_READ
Figure 44. Reset Timings
SYMBOL
t_RST1
t_RST2
PARAMETER
NRST active low pulse width
NRST inactive or I²C reset
event to MEMORY READ end
LIMIT
1 µs min + value on DELAY register.
25 µs max
Table 6. Hardware Reset, Power-On Reset (POR) and Software Reset: Registers After Reset
Hex Address
0x00
0x06
0x07
0x0D
0x0E
0x0F
0x010
0x011
0x012
0x018
0x019
0x01F
0x21
0x22
0x2E
0xDD
Register
VSET_B0
FPWM
BUCK0_CTRL
FLAGS_0
FLAGS_1
INT_MASK0
GENERAL
RESET
DELAY_BUCK0
CHIP_ID
PFM_LEV_B0
PHASE_LEV_B0
SEL_I_LOAD
LOAD_CURR
INT_MASK_2
LOCK_REG
Software Reset
I²C RESET
All bits retained
All bits cleared
All bits cleared
All bits retained
All bits retained
All bits cleared
All bits cleared
N/A
All bits cleared
All bits cleared
All bits cleared
All bits retained
All bits cleared
All bits retained
Hardware Reset
NRST LOW⁽¹⁾
All bits retained
All bits cleared
All bits cleared
All bits retained
All bits retained
All bits cleared
All bits cleared
All bits cleared
All bits cleared
Read Only
All bits cleared
All bits cleared
All bits retained
Read Only
All bits cleared
All bits retained
Power-On Reset
VIOSYS LOW
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
(1) Reset will take effect upon complete of the power-down sequence.
Diagnosis and Protection Features
The LP8755 is capable of providing two levels of protection features: Warnings for diagnosis and faults which are
causing the converters to shut down. When the device detects warning or fault conditions, the LP8755 sets the
flag bits indicating which fault or warning conditions have occurred; the INT pin will be pulled low. INT will be
released again after a clear of flags is complete. The flag bits are persistent over reset to allow for the system to
identify what was causing the interrupt and/or converter shutdown.
Also, the LP8755 has a soft-start circuit that limits in-rush current during startup. The output voltage increase rate
is 30 mV/μsec (default) during soft-start.
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