LM3S1811 Datasheet, PDF (5/946 Pages) Texas Instruments – Stellaris® LM3S1811 Microcontroller

Stellaris^® LM3S1811 Microcontroller
6
Hibernation Module .............................................................................................. 274
6.1 Block Diagram ............................................................................................................ 275
6.2 Signal Description ....................................................................................................... 275
6.3 Functional Description ................................................................................................. 276
6.3.1 Register Access Timing ............................................................................................... 276
6.3.2 Hibernation Clock Source ............................................................................................ 277
6.3.3 System Implementation ............................................................................................... 278
6.3.4 Battery Management ................................................................................................... 279
6.3.5 Real-Time Clock .......................................................................................................... 279
6.3.6 Battery-Backed Memory .............................................................................................. 280
6.3.7 Power Control Using HIB ............................................................................................. 280
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 280
6.3.9 Initiating Hibernate ...................................................................................................... 280
6.3.10 Waking from Hibernate ................................................................................................ 280
6.3.11 Interrupts and Status ................................................................................................... 281
6.4 Initialization and Configuration ..................................................................................... 281
6.4.1 Initialization ................................................................................................................. 281
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 282
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 282
6.4.4 External Wake-Up from Hibernation .............................................................................. 283
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 283
6.5 Register Map .............................................................................................................. 283
6.6 Register Descriptions .................................................................................................. 284
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 301
Block Diagram ............................................................................................................ 301
Functional Description ................................................................................................. 301
SRAM ........................................................................................................................ 302
ROM .......................................................................................................................... 302
Flash Memory ............................................................................................................. 304
Register Map .............................................................................................................. 309
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 310
Memory Register Descriptions (System Control Offset) .................................................. 322
8
Micro Direct Memory Access (μDMA) ................................................................ 338
8.1 Block Diagram ............................................................................................................ 339
8.2 Functional Description ................................................................................................. 339
8.2.1 Channel Assignments .................................................................................................. 340
8.2.2 Priority ........................................................................................................................ 341
8.2.3 Arbitration Size ............................................................................................................ 341
8.2.4 Request Types ............................................................................................................ 341
8.2.5 Channel Configuration ................................................................................................. 342
8.2.6 Transfer Modes ........................................................................................................... 344
8.2.7 Transfer Size and Increment ........................................................................................ 352
8.2.8 Peripheral Interface ..................................................................................................... 352
8.2.9 Software Request ........................................................................................................ 352
8.2.10 Interrupts and Errors .................................................................................................... 353
8.3 Initialization and Configuration ..................................................................................... 353
8.3.1 Module Initialization ..................................................................................................... 353
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 353
January 21, 2012
5
Texas Instruments-Production Data