LM3S1811 Datasheet, PDF (3/946 Pages) Texas Instruments – Stellaris® LM3S1811 Microcontroller

Stellaris^® LM3S1811 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 27
About This Document .................................................................................................................... 38
Audience .............................................................................................................................................. 38
About This Manual ................................................................................................................................ 38
Related Documents ............................................................................................................................... 38
Documentation Conventions .................................................................................................................. 39
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
Architectural Overview .......................................................................................... 41
Overview ...................................................................................................................... 41
Target Applications ........................................................................................................ 43
Features ....................................................................................................................... 43
ARM Cortex-M3 Processor Core .................................................................................... 43
On-Chip Memory ........................................................................................................... 45
External Peripheral Interface ......................................................................................... 46
Serial Communications Peripherals ................................................................................ 48
System Integration ........................................................................................................ 51
Analog .......................................................................................................................... 56
JTAG and ARM Serial Wire Debug ................................................................................ 58
Packaging and Temperature .......................................................................................... 58
Hardware Details .......................................................................................................... 58
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 60
Block Diagram .............................................................................................................. 61
Overview ...................................................................................................................... 62
System-Level Interface .................................................................................................. 62
Integrated Configurable Debug ...................................................................................... 62
Trace Port Interface Unit (TPIU) ..................................................................................... 63
Cortex-M3 System Component Details ........................................................................... 63
Programming Model ...................................................................................................... 64
Processor Mode and Privilege Levels for Software Execution ........................................... 64
Stacks .......................................................................................................................... 64
Register Map ................................................................................................................ 65
Register Descriptions .................................................................................................... 66
Exceptions and Interrupts .............................................................................................. 79
Data Types ................................................................................................................... 79
Memory Model .............................................................................................................. 79
Memory Regions, Types and Attributes ........................................................................... 81
Memory System Ordering of Memory Accesses .............................................................. 81
Behavior of Memory Accesses ....................................................................................... 82
Software Ordering of Memory Accesses ......................................................................... 82
Bit-Banding ................................................................................................................... 84
Data Storage ................................................................................................................ 86
Synchronization Primitives ............................................................................................. 86
Exception Model ........................................................................................................... 87
Exception States ........................................................................................................... 88
Exception Types ............................................................................................................ 88
Exception Handlers ....................................................................................................... 91
January 21, 2012
3
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