LM3S1811 Datasheet, PDF (380/946 Pages) Texas Instruments – Stellaris® LM3S1811 Microcontroller

Micro Direct Memory Access (μDMA)
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAENASET register.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
CLR[n]
Type
WO
Reset
-
Description
Clear Channel [n] Enable Clear
Value Description
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the
DMAENASET register meaning that channel [n] is disabled for
μDMA transfers.
Note: The controller disables a channel when it completes the μDMA
cycle.
380
January 21, 2012
Texas Instruments-Production Data