DS92LV1021A_14 Datasheet, PDF (5/18 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer

DS92LV1021A
www.ti.com
SNLS151G – OCTOBER 2002 – REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾
Symbol
Parameter
Conditions
Min
Typ
t_LLHT
t_LHLT
Bus LVDS Low-to-High
Transition Time
Bus LVDS High-to-Low
Transition Time
R_L = 27Ω, Figure 2,
C_L=10pF to GND
0.31
0.30
t_DIS
DIN (0-9) Setup to
TCLK
See Figure 4,
0
t_DIH
DIN (0-9) Hold from
TCLK
R_L = 27Ω,
C_L=10pF to GND
4.0
t_HZD
DO ± HIGH to
TRI-STATE Delay
3.5
t_LZD
DO ± LOW to TRI-
STATE Delay
See Figure 5 ,⁽³⁾,
2.9
t_ZHD
DO ± TRI-STATE to
HIGH Delay
R_L = 27Ω,
C_L=10pF to GND
2.5
t_ZLD
DO ± TRI-STATE to
LOW Delay
2.7
t_SPW
t_PLD
t_SD
t_BIT
t_DJIT
SYNC Pulse Width
Serializer PLL Lock
Time
Serializer Delay
Bus LVDS Bit Width
Deterministic Jitter
See Figure 7,
R_L = 27Ω
See Figure 6,
R_L = 27Ω
See Figure 8 , R_L = 27Ω
R_L = 27Ω,
C_L=10pF to GND
R_L = 27Ω,
C_L=10pF to GND, ⁽⁴⁾
f = 40 MHz
f = 16 MHz
5*t_TCP
510*t_TCP
t_TCP+1.0
−320
−800
t_TCP + 2.0
t_CLK / 12
−110
−160
Max
0.75
0.75
10
10
10
10
2049*t_TCP
t_TCP+4.0
150
380
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
(1) Typical values are given for V_CC = 3.3V and T_A = +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(4) t_DJIT specifications are specified by design using statistical analysis.
AC Timing Diagrams and Test Circuits
Figure 1. “Worst Case” Serializer ICC Test Pattern
Figure 2. Serializer Bus LVDS Output Load and Transition Times
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