DS92LV1021A_14 Datasheet, PDF (3/18 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer

DS92LV1021A
www.ti.com
SNLS151G – OCTOBER 2002 – REVISED APRIL 2013
Ideal Crossing Point
The ideal crossing point is the best case start and stop point for a normalized bit. Each ideal crossing point is
found by dividing the clock period by twelve--two clock bits plus ten data bits. For example, a 40 MHz clock has a
period of 25ns. The 25ns divided by 12 bits is approximately 2.08ns. This means that each bit width is
approximately 2.08ns, and the ideal crossing points occur every 2.08ns. For a graphical representation, please
see Figure 9.
Resynchronization
The Deserializer LOCK pin driven low indicates that the Deserializer PLL is locked to the embedded clock edge.
If the Deserializer loses lock, the LOCK output will go high and the outputs (including RCLK) will be TRI-STATE.
The LOCK pin must be monitored by the system to detect a loss of synchronization, and the system must decide
if it is necessary to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. There are multiple approaches
possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync
request of the Serializer (SYNC1 or SYNC2). At the time of publication, other than the DS92LV1210, all other
Deserializers from TI have random lock capability. This feature does not require the system user to send SYNC
patterns upon loss of lock. However, lock times can only be specified with transmission of SYNC patterns. Dual
SYNC pins are provided for multiple control in a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The device enters Powerdown when the PWRDN pin is driven low on the
Serializer. In Powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing
supply current into the milliamp range. To exit Powerdown, PWRDN must be driven high.
Both the Serializer and Deserializer must reinitialize and resynchronize before data can be transferred. The
Deserializer will initialize and assert LOCK high until it is locked to the Bus LVDS clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN pin is driven low. This will TRI-STATE both driver output
pins (DO+ and DO−). When DEN is driven high, the serializer will return to the previous state as long as all other
control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings⁽¹⁾⁽²⁾
Supply Voltage (V_CC)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
Bus LVDS Receiver Input Voltage
Bus LVDS Driver Output Voltage
Bus LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity @ 25°C Package:
28L SSOP
Package Derating: 28L SSOP
ESD Rating (HBM)⁽³⁾
−0.3V to +4V
−0.3V to (V_CC +0.3V)
−0.3V to (V_CC +0.3V)
−0.3V to +3.9V
−0.3V to +3.9V
Continuous
+150°C
−65°C to +150°C
+260°C
1.27 W
10.2 mW/°C above +25°C
>2.0kV
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) With a limited Engineering sample size, ESD (HBM) testing passed 2.5kV
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV1021A
Submit Documentation Feedback
3