DS92LV1021A_14 Datasheet, PDF (2/18 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer

DS92LV1021A
SNLS151G – OCTOBER 2002 – REVISED APRIL 2013
www.ti.com
Functional Description
The DS92LV1021A is an upgrade to the DS92LV1021. The DS92LV1021A no longer has a power-up sequence
requirement. Like the DS92LV1021, the DS92LV1021A is a 10-bit Serializer designed to transmit data over a
differential backplane at clock speeds from 16 to 40MHz. It may also be used to drive data over Unshielded
Twisted Pair (UTP) cable.
The DS92LV1021A can be used with any of TI’s 10-bit BLVDS Deserializers (DS92LV1212A for example) and
has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states:
Powerdown and TRI-STATE.
The following sections describe each active and passive state.
Initialization
Before data can be transferred, the Serializer must be initialized. Initialization refers to synchronization of the
Serializer’s PLL to a local clock.
When V_CC is applied to the Serializer, the outputs are held in TRI-STATE and internal circuitry is disabled by on-
chip power-on circuitry. When V_CC reaches V_CC OK (2.5V) the Serializer’s PLL begins locking to the local clock.
The local clock is the transmit clock, TCLK, provided by the source ASIC or other device.
Once the PLL locks to the local clock, the Serializer is ready to send data or SYNC patterns, depending on the
levels of the SYNC1 and SYNC2 inputs. The SYNC pattern is composed of six ones and six zeros switching at
the input clock rate.
Control of the SYNC pins is left to the user. One recommendation is a direct feedback loop from the LOCK pin.
Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low.
Data Transfer
After initialization, the Serializer inputs DIN0–DIN9 may be used to input data to the Serializer. Data is clocked
into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the TCLK_R/F
pin. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the
SYNC inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of the clock edge.
A start bit and a stop bit, appended internally, frame the data bits in the register. The start bit is always high and
the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream.
Serialized data and clock bits (10+2 bits) are transmitted from the serial data output (DO±) at 12 times the TCLK
frequency. For example, if TCLK is 40 MHz, the serial rate is 40 × 12 = 480 Mega bits per second. Since only 10
bits are from input data, the serial “payload” rate is ten times the TCLK frequency. For instance, if TCLK = 40
MHz, the payload data rate is 40 × 10 = 400 Mbps. TCLK is provided by the data source and must be in the
range of 16 MHz to 40 MHz nominal.
The outputs (DO±) can drive a backplane or a point-to-point connection. The outputs transmit data when the
enable pin (DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are low. The DEN pin may be used to TRI-
STATE the outputs when driven low.
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