DS90CR583_13 Datasheet, PDF (5/13 Pages) Texas Instruments – LVDS 24-Bit Color Flat Panel Display (FPD) Link- 65 MHz

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OBSOLETE
AC Timing Diagrams
DS90CR583, DS90CR584
SNLS110B – JULY 1997 – REVISED APRIL 2013
Figure 3. “Worst Case” Test Pattern
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 4 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern
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