DS90CR216MTDX Datasheet, PDF (5/23 Pages) Texas Instruments – DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz

DS90CR215, DS90CR216
www.ti.com
SNLS129D – MARCH 1999 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
TPPos0
Parameter
Transmitter Output Pulse Position for Bit0 ⁽²⁾
(Figure 20)
f = 66 MHz
Min
Typ
−0.4
0
TPPos1
Transmitter Output Pulse Position for Bit1
1.8
2.2
TPPos2
Transmitter Output Pulse Position for Bit2
4.0
4.4
TPPos3
Transmitter Output Pulse Position for Bit3
6.2
6.6
TPPos4
Transmitter Output Pulse Position for Bit4
8.4
8.8
TPPos5
Transmitter Output Pulse Position for Bit5
10.6
11.0
TPPos6
Transmitter Output Pulse Position for Bit6
12.8
13.2
TCIP
TxCLK IN Period (Figure 10)
15
T
TCIH
TxCLK IN High Time (Figure 10)
0.35T
0.5T
TCIL
TxCLK IN Low Time (Figure 10)
0.35T
0.5T
TSTC
TxIN Setup to TxCLK IN (Figure 10)
2.5
THTC
TxIN Hold to TxCLK IN (Figure 10)
0
TCCD
TxCLK IN to TxCLK OUT Delay @ 25°C,V_CC=3.3V (Figure 12)
3
3.7
TPLLS
Transmitter Phase Lock Loop Set (Figure 14)
TPDD
Transmitter Powerdown Delay (Figure 18)
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Max
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
5.5
10
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 7)
CHLT
RSPos0
CMOS/TTL High-to-Low Transition Time (Figure 7)
Receiver Input Strobe Position for Bit 0 ⁽¹⁾(Figure 21)
f = 40 MHz
1.0
RSPos1
Receiver Input Strobe Position for Bit 1
4.5
RSPos2
Receiver Input Strobe Position for Bit 2
8.1
RSPos3
Receiver Input Strobe Position for Bit 3
11.6
RSPos4
Receiver Input Strobe Position for Bit 4
15.1
RSPos5
Receiver Input Strobe Position for Bit 5
18.8
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 6
Receiver Input Strobe Position for Bit 0 ⁽²⁾(Figure 21)
22.5
f = 66 MHz
0.7
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin ⁽³⁾(Figure 22)
13.9
f = 40 MHz
490
f = 66 MHz
400
RCOP
RxCLK OUT Period (Figure 11)
15
RCOH
RxCLK OUT High Time (Figure 11)
f = 40 MHz
6.0
f = 66 MHz
4.0
Typ Max Units
2.2
5.0
ns
2.2
5.0
ns
1.4 2.15 ns
5.0
5.8
ns
8.5 9.15 ns
11.9 12.6 ns
15.6 16.3 ns
19.2 19.9 ns
22.9 23.6 ns
1.1
1.4
ns
3.3
3.6
ns
5.5
5.8
ns
7.7
8.0
ns
9.9 10.2 ns
12.1 12.4 ns
14.3 14.6 ns
ps
ps
T
50
ns
10.0
ns
6.1
ns
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
(3) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS
interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter less than 250 ps.
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