DS90CR216MTDX Datasheet, PDF (15/23 Pages) Texas Instruments – DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz

DS90CR215, DS90CR216
www.ti.com
SNLS129D – MARCH 1999 – REVISED APRIL 2013
TERMINATION
Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK
chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination resistor should be selected to match the differential
mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 23 shows an example. No additional
pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface
mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These
resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively
terminate the differential lines.
Figure 23. LVDS Serialized Link Termination
DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each V_CC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01μF and 0.001 μF. An example is shown in Figure 24. The designer should employ wide traces for
power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL V_CC should receive the most filtering/bypassing. Next would be the LVDS
V_CC pins and finally the logic V_CC pins.
Figure 24. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER
The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS
interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example,
a 66 MHz clock has a period of 15 ns which results in a data bit width of 2.16 ns. Differential skew (Δt within one
differential pair), interconnect skew (Δt of one differential pair to another) and clock jitter will all reduce the
available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input
to the transmitter be a clean low noise signal. Individual bypassing of each V_CC to ground will minimize the noise
passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-
to-channel skew and interconnect skew as a part of the overall jitter/skew budget.
Copyright © 1999–2013, Texas Instruments Incorporated
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