|
DS90CR216MTDX Datasheet, PDF (12/23 Pages) Texas Instruments – DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz | |||
|
◁ |
DS90CR215, DS90CR216
SNLS129D â MARCH 1999 â REVISED APRIL 2013
www.ti.com
CâSetup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
TpposâTransmitter output pulse position (min and max)
RSKM ⥠Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable SkewâtypicaIIy 10 psâ40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps
ISI is dependent on interconnect length; may be zero
Figure 22. Receiver LVDS Input Skew Margin
12
Submit Documentation Feedback
Copyright © 1999â2013, Texas Instruments Incorporated
Product Folder Links: DS90CR215 DS90CR216
|
▷ |