DS90CF583_13 Datasheet, PDF (5/13 Pages) Texas Instruments – LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz

OBSOLETE
DS90CF583, DS90CF584
www.ti.com
SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
TPPos4 Transmitter Output Pulse Position 4
8.30
TPPos5 Transmitter Output Pulse Position 5
10.40
TPPos6 Transmitter Output Pulse Position 6
12.70
Typ
4/7 T_clk
5/7 T_clk
6/7 T_clk
Max
9.00
11.10
13.40
Units
ns
ns
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 6)
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 6)
RCOP
RxCLK OUT Period
RCOH
RxCLK OUT High Time
f = 65 MHz
RCOL
RxCLK OUT Low Time
f = 65 MHz
RSRC
RxOUT Setup to RxCLK OUT
f = 65 MHz
RHRC
RxOUT Hold to RxCLK OUT
f = 65 MHz
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 5.0V
(Figure 12)
RPLLS
RSKM
RPDD
Receiver Phase Lock Loop Set (Figure 14)
RxIN Skew Margin ⁽¹⁾ (Figure 16)
Receiver Powerdown (Figure 19)
V_CC = 5V, T_A =25°C
Min Typ Max Units
2.5
4.0
ns
2.0
3.5
ns
15
T
50
ns
7.8
9
ns
3.8
5
ns
2.5 4.2
ns
4.0 5.2
ns
6.4
10.7
ns
10
ms
600
ps
1
μs
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter
output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on
type/length and source clock (TxCLK IN) jitter.RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
Copyright © 1996–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS90CF583 DS90CF584