DS90CF583_13 Datasheet, PDF (10/13 Pages) Texas Instruments – LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz

DS90CF583, DS90CF584
SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013
OBSOLETE
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Figure 18. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF583)
Figure 19. Receiver Powerdown Delay
Figure 20. Transmitter Powerdown Delay
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
DS90CF583 Pin Descriptions—FPD Link Transmitter
I/O No.
Description
I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME, DRDY and
CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL)
O 4 Positive LVDS differential data output
O 4 Negative LVDS differential data output
I 1 TTL level clock input. The falling edge acts as data strobe
O 1 Positive LVDS differential clock output
O 1 Negative LVDS differential clock output
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down
I 4 Power supply pins for TTL inputs
10
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