DS90CF583_13 Datasheet, PDF (4/13 Pages) Texas Instruments – LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz

DS90CF583, DS90CF584
OBSOLETE
SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
I_OZ
Output TRI-STATE Current
LVDS RECEIVER DC SPECIFICATIONS
Power Down = 0V, V_OUT = 0V or V_CC
V_TH
Differential Input High Threshold
V_TL
Differential Input Low Threshold
I_IN
Input Current
TRANSMITTER SUPPLY CURRENT
V_CM = +1.2V
V_IN = +2.4V
V_IN = 0V
V_CC = 5.5V
I_CCTW
Transmitter Supply Current,
Worst Case
R_L = 100Ω, C_L = 5 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figure 3, Figure 5)
f = 65 MHz
I_CCTG
Transmitter Supply Current,
16 Grayscale
R_L = 100Ω, C_L = 5 pF,
16 Grayscale Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figure 4, Figure 5)
f = 65 MHz
I_CCTZ
Transmitter Supply Current,
Power Down
Power Down = Low
RECEIVER SUPPLY CURRENT
I_CCRW
Receiver Supply Current,
Worst Case
C_L = 8 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figure 3, Figure 6)
f = 65 MHz
I_CCRG
Receiver Supply Current,
16 Grayscale
C_L = 8 pF,
16 Grayscale Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figure 4, Figure 6)
f = 65 MHz
I_CCRZ
Receiver Supply Current,
Power Down
Power Down = Low
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Min Typ Max Units
±1 ±10 μA
−100
+100 mV
mV
±10 μA
±10 μA
49 63 mA
51 64 mA
70 84 mA
40 55 mA
41 55 mA
55 67 mA
1 25 μA
64 77 mA
70 85 mA
110 140 mA
35 55 mA
37 55 mA
55 67 mA
1 10 μA
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 5)
LHLT
LVDS High-to-Low Transition Time (Figure 5)
TCIT
TCCS
TxCLK IN Transition Time (Figure 7)
TxOUT Channel-to-Channel Skew ⁽¹⁾ (Figure 8)
TCCD
TxCLK IN to TxCLK OUT Delay @ 25°C, V_CC = 5.0V
3.5
(Figure 11)
TCIP
TxCLK IN Period (Figure 9)
15
TCIH
TxCLK IN High Time (Figure 9)
0.35T
TCIL
TxCLK IN Low Time (Figure 9)
0.35T
TSTC
TxIN Setup to TxCLK IN (Figure 9 )
f = 65 MHz
5
THTC
TxIN Hold to TxCLK IN (Figure 9)
2.5
TPDD
Transmitter Powerdown Delay (Figure 20)
TPLLS Transmitter Phase Lock Loop Set (Figure 13)
TPPos0 Transmitter Output Pulse Position 0 (Figure 15)
−0.30
TPPos1 Transmitter Output Pulse Position 1
1.70
TPPos2 Transmitter Output Pulse Position 2
3.60
TPPos3 Transmitter Output Pulse Position 3
5.90
Typ
0.75
0.75
T
0.5T
0.5T
3.5
1.5
0
1/7 T_clk
2/7 T_clk
3/7 T_clk
Max
Units
1.5
ns
1.5
ns
8
ns
350
ps
8.5
ns
50
ns
0.65T
ns
0.65T
ns
ns
ns
100
ns
10
ms
0.30
ns
2.50
ns
4.50
ns
6.75
ns
(1) This limit based on bench characterization.
4
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