DS90CF384AQ Datasheet, PDF (5/12 Pages) Texas Instruments – DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz

AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern (Note 5)
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FIGURE 2. “16 Grayscale” Test Pattern (Note 6, Note 7, Note 8)
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Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figure 1 and Figure 2 shows a falling edge data strobe (TxCLK IN / RxCLK OUT).
Note 8: Recommended pin to signal mapping. Application may choose to define differently, check compatibility with source.
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