DS90CF384AQ Datasheet, PDF (2/12 Pages) Texas Instruments – DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz

DS90CF384AQ
August 1, 2011
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link
- 65 MHz
General Description
The DS90CF384AQ receiver converts the four LVDS data
streams at up to 1.8 Gbps throughput (227 Megabytes/sec
bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data.
In a Display application, the 28 bits include: 24 bits of RGB
data and up to 4 bits of video control (Hsync, Vsync, DE and
CNTL).
The DS90CF384AQ device is enhanced over prior generation
FPD-Link receivers, provides a wider data valid time on the
receiver output and is offered as an AEC-Q100 grade 3 de-
vice.
FPD-Link is an ideal means to solve EMI and cable size prob-
lems associated with wide, high speed LVCMOS/LVTTL in-
terfaces.
Features
■ ^{Automotive grade device, AEC-Q100 grade 3 qualified}
■ ^{Operating Temperature Range: –40°C to +85°C}
■ ^{20 to 65 MHz shift clock support}
■ ^{50% duty cycle on receiver output clock}
■ ^{Best–in–Class Set & Hold Times on RxOUTPUTs}
■ ^{Rx power consumption <142 mW (typ) @65MHz}
Grayscale
■ ^{Rx Power-down mode <200μW (max)}
■ ^{ESD rating >7 kV (HBM), >700V (EIAJ)}
■ ^{Supports VGA, SVGA, XGA and Dual Pixel SXGA.}
■ ^{PLL requires no external components}
■ ^{Compatible with TIA/EIA-644 LVDS standard}
■ ^{Low profile 56-lead TSSOP package}
Block Diagram
DS90CF384AQ
Order Number DS90CF384AQMT
See NS Package Number MTD56
30161127
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