DS90CF384AQ Datasheet, PDF (4/12 Pages) Texas Instruments – DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3 )
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3 )
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9 )
f = 25 MHz
1.20
RSPos1 Receiver Input Strobe Position for Bit 1
6.91
RSPos2 Receiver Input Strobe Position for Bit 2
12.62
RSPos3 Receiver Input Strobe Position for Bit 3
18.33
RSPos4 Receiver Input Strobe Position for Bit 4
24.04
RSPos5 Receiver Input Strobe Position for Bit 5
29.75
RSPos6 Receiver Input Strobe Position for Bit 6
35.46
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9 )
f = 65 MHz
0.7
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
RSPos5 Receiver Input Strobe Position for Bit 5
11.7
RSPos6 Receiver Input Strobe Position for Bit 6
13.9
RSKM
RxIN Skew Margin(Note 4) (Figure 10 )
f = 25 MHz
750
f = 65 MHz
500
RCOP
RxCLK OUT Period (Figure 4)
15
RCOH RxCLK OUT High Time (Figure 4)
f = 65 MHz
5.0
RCOL
RxCLK OUT Low Time (Figure 4)
5.0
RSRC
RxOUT Setup to RxCLK OUT (Figure 4)
4.5
RHRC
RxOUT Hold to RxCLK OUT (Figure 4)
4.0
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 3.3V (Figure 5 )
3.5
RPLLS Receiver Phase Lock Loop Set (Figure 6 )
RPDD
Receiver Power Down Delay (Figure 8 )
Typ
2
1.8
1.96
7.67
13.38
19.09
24.80
30.51
36.22
1.1
3.3
5.5
7.7
9.9
12.1
14.3
T
7.6
6.3
7.3
6.3
5.0
Max
5
5
2.82
8.53
14.24
19.95
25.66
31.37
37.08
1.4
3.6
5.8
8.0
10.2
12.4
14.6
50
9.0
9.0
7.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ms
μs
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383B transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). The RSKM will change when different
transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less
than 250 ps).
3
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