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| DS90CF364A_15 Datasheet, PDF (5/22 Pages) Texas Instruments – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65MHz | |||
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www.ti.com
DS90CF364A, DS90CF384A
SNLS040I â JUNE 2000 â REVISED APRIL 2013
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a âtypicalâ LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. â16 Grayscaleâ Test Pattern (DS90CF384A)
Copyright © 2000â2013, Texas Instruments Incorporated
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Product Folder Links: DS90CF364A DS90CF384A
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