DS90CF364A_15 Datasheet, PDF (3/22 Pages) Texas Instruments – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65MHz

DS90CF364A, DS90CF384A
www.ti.com
SNLS040I – JUNE 2000 – REVISED APRIL 2013
Electrical Characteristics⁽¹⁾ (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
LVDS RECEIVER DC SPECIFICATIONS
V_TH
Differential Input High Threshold
V_TL
Differential Input Low Threshold
I_IN
Input Current
RECEIVER SUPPLY CURRENT⁽²⁾
V _CM = +1.2V
V _IN = +2.4V, V_CC = 3.6V
V _IN = 0V, V_CC = 3.6V
ICCRW Receiver Supply Current Worst Case
C_L = 8 pF,
Worst Case Pattern,
DS90CF384A (Figure 3
Figure 6)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
ICCRW Receiver Supply Current Worst Case
C_L = 8 pF,
Worst Case Pattern,
DS90CF364A (Figure 3
Figure 6)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
ICCRG Receiver Supply Current, 16 Grayscale
C_L = 8 pF,
f = 32.5 MHz
16 Grayscale Pattern,
(Figure 4 Figure 5 Figure 6)
f = 37.5 MHz
f = 65 MHz
ICCRZ Receiver Supply Current
Power Down
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
Min
−100
Typ Max Units
+100 mV
mV
±10
μA
±10
μA
49
65
mA
53
70
mA
81
105 mA
49
55
mA
53
60
mA
78
90
mA
28
45
mA
30
47
mA
43
60
mA
10
55
μA
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except V_OD and ΔV _OD).
Receiver Switching Characteristics⁽¹⁾
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 6)
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 6)
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 13,
f = 25 MHz
1.20
Figure 14)
RSPos1 Receiver Input Strobe Position for Bit 1
6.91
RSPos2 Receiver Input Strobe Position for Bit 2
12.62
RSPos3 Receiver Input Strobe Position for Bit 3
18.33
RSPos4 Receiver Input Strobe Position for Bit 4
24.04
RSPos5 Receiver Input Strobe Position for Bit 5
29.75
RSPos6 Receiver Input Strobe Position for Bit 6
35.46
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 13,
f = 65 MHz
0.7
Figure 14)
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
RSPos5 Receiver Input Strobe Position for Bit 5
11.7
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin ⁽²⁾ (Figure 15)
13.9
f = 25 MHz
750
f = 65 MHz
500
Typ
2
1.8
1.96
7.67
13.38
19.09
24.80
30.51
36.22
1.1
3.3
5.5
7.7
9.9
12.1
14.3
Max
5
5
2.82
8.53
14.24
19.95
25.66
31.37
37.08
1.4
3.6
5.8
8.0
10.2
12.4
14.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
(1) Typical values are given for V_CC = 3.3V and T_A = +25C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the
DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window -
RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Copyright © 2000–2013, Texas Instruments Incorporated
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