DS90CF364A_15 Datasheet, PDF (4/22 Pages) Texas Instruments – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65MHz

DS90CF364A, DS90CF384A
SNLS040I – JUNE 2000 – REVISED APRIL 2013
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Receiver Switching Characteristics⁽¹⁾ (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
RCOP
RxCLK OUT Period (Figure 7)
15
T
50
ns
RCOH
RxCLK OUT High Time (Figure 7)
f = 65 MHz
5.0
7.6
9.0
ns
RCOL
RxCLK OUT Low Time (Figure 7)
5.0
6.3
9.0
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 7)
4.5
7.3
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 7)
4.0
6.3
ns
RCCD
RPLLS
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 3.3V (Figure 8)
Receiver Phase Lock Loop Set (Figure 9)
3.5
5.0
7.5
ns
10
ms
RPDD
Receiver Power Down Delay (Figure 12 )
1
μs
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
4
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