DS90CF363B_13 Datasheet, PDF (5/15 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

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DS90CF363B
SNLS180D – JULY 2004 – REVISED APRIL 2013
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. “16 Grayscale” Test Pattern
Figure 4. DS90CF363B (Transmitter) LVDS Output Load
Figure 5. DS90CF363B (Transmitter) LVDS Transition Times
Figure 6. DS90CF363B (Transmitter) Input Clock Transition Time
Copyright © 2004–2013, Texas Instruments Incorporated
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