DS90CF363B_13 Datasheet, PDF (4/15 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

DS90CF363B
SNLS180D – JULY 2004 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TPPos0
TPPos1
Parameter
Transmitter Output Pulse Position for Bit 0 (Figure 12 )⁽¹⁾
Transmitter Output Pulse Position for Bit 1
Min
Typ
f = 40 −0.25
0
MHz
3.32
3.57
TPPos2 Transmitter Output Pulse Position for Bit 2
6.89
7.14
TPPos3 Transmitter Output Pulse Position for Bit 3
10.46 10.71
TPPos4 Transmitter Output Pulse Position for Bit 4
14.04 14.29
TPPos5 Transmitter Output Pulse Position for Bit 5
17.61 17.86
TPPos6
TPPos0
TPPos1
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 12 )⁽¹⁾
Transmitter Output Pulse Position for Bit 1
f=
25MHz
21.18
−0.45
5.26
21.43
0
5.71
TPPos2 Transmitter Output Pulse Position for Bit 2
10.98 11.43
TPPos3 Transmitter Output Pulse Position for Bit 3
16.69 17.14
TPPos4 Transmitter Output Pulse Position for Bit 4
22.41 22.86
TPPos5 Transmitter Output Pulse Position for Bit 5
28.12 28.57
TPPos6 Transmitter Output Pulse Position for Bit 6
33.84 34.29
TSTC
TxIN Setup to TxCLK IN (Figure 7 )
2.5
THTC
TxIN Hold to TxCLK IN (Figure 7 )
0.5
TCCD
SSCG
TxCLK IN to TxCLK OUT Delay (Figure 8 ) 50% duty cycle input clock is assumed, T
A^{= −10°C, and 65MHz for " Min ", T} A ^{= 70°C, and 25MHz for " Max ", V}CC ^{= 3.6V}
Spread Spectrum Clock support; Modulation frequency with a linear
profile ⁽²⁾
f = 25
MHz
3.011
100KHz ±
2.5%/−5%
f = 40
MHz
100KHz ±
2.5%/−5%
f = 65
MHz
100KHz ±
2.5%/−5%
TPLLS
Transmitter Phase Lock Loop Set (Figure 9 )
TPDD
Transmitter Power Down Delay (Figure 11 )
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Max
+0.25
3.82
7.39
10.96
14.54
18.11
21.68
+0.45
6.16
11.88
17.59
23.31
29.02
34.74
6.082
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ms
100
ns
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
AC Timing Diagrams
Figure 2. “Worst Case” Test Pattern
4
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