DS80PCI402 Datasheet, PDF (5/39 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

Pin Name
Pin Number I/O, Type
Pin Description
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis
of the A/B sides as shown in . The pins are only active when
ENSMB is de-asserted (low). Each of the 4 A/B channels have
the same level unless controlled by the SMBus control
registers. When ENSMB goes high the SMBus registers
provide independent control of each lane. The DEMA[1:0]
pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins
are converted to AD0, AD1 inputs. See Table 3: Output
Voltage and De-emphasis Settings.
RATE
21
I, 4-LEVEL, RATE control pin selects GEN 1,2 and GEN 3 operating
LVCMOS
modes.
Tie 1kΩ to GND = GEN 1,2
Float = Auto Rate select
Tie 20kΩ to GND = GEN 3 without De-emphasis
Tie 1kΩ to VDD = GEN 3 with De-emphasis
SD_TH
26
I, 4-LEVEL, Controls the internal Signal Detect Threshold.
LVCMOS
See Table 5: Signal Detect Threshold Level.
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL, The RXDET pin controls the receiver detect function.
LVCMOS
Depending on the input level, a 50Ω or >50KΩ termination to
the power rail is enabled.
See Table 4: RX-Detect Settings.
LPBK
23
I, 4-LEVEL, Controls the loopback function
LVCMOS
Tie 1kΩ to GND = Root Complex Loopback (INA_n to
OUTB_n
Float = Normal Operation
Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
VDD_SEL
25
I, FLOAT
Controls the internal regulator
Float = 2.5V mode
Tie GND = 3.3V mode
PRSNT
52
I, LVCMOS Cable Present Detect input. high when a cable is not present
per PCIe Cabling Spec. 1.0. Puts part into low power mode.
When low (normal operation) part is enabled. See Table 4:
RX-Detect Settings.
Outputs
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
Power
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating.
VDD
9, 14,36, 41, Power
51
Power supply pins CML/analog
2.5V mode, connect to 2.5V
3.3V mode, connect 0.1 uF cap to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad).
Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not
guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
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