DS80PCI402 Datasheet, PDF (4/39 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

Pin Descriptions
Pin Name
Pin Number I/O, Type
Differential High Speed I/O's
INB_0+, INB_0- ,
INB_1+, INB_1-,
INB_2+, INB_2-,
INB_3+, INB_3-
45, 44, 43, 42 I
40, 39, 38, 37
OUTB_0+, OUTB_0-, 1, 2, 3, 4
O
OUTB_1+, OUTB_1-, 5, 6, 7, 8
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-
INA_0+, INA_0- ,
INA_1+, INA_1-,
INA_2+, INA_2-,
INA_3+, INA_3-
10, 11, 12, 13 I
15, 16, 17, 18
OUTA_0+, OUTA_0-, 35, 34, 33, 32 O
OUTA_1+, OUTA_1-, 31, 30, 29, 28
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS,
O, OPEN
Drain
SDA
AD0-AD3
49
I, LVCMOS,
O, OPEN
Drain
54, 53, 47, 46 I, LVCMOS
READ_EN
26
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I, LVCMOS
I, 4-LEVEL,
LVCMOS
Pin Description
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INB_n+ to VDD and INB_n- to VDD when enabled.
Inverting and non-inverting 50Ω driver outputs with de-
emphasis. Compatible with AC coupled CML inputs.
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INA_n+ to VDD and INA_n- to VDD when enabled.
Inverting and non-inverting 50Ω driver outputs with de-
emphasis. Compatible with AC coupled CML inputs.
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB Master or Slave mode
SMBUS clock input pin is enabled (slave mode).
Clock output when loading EEPROM configuration (master
mode).
ENSMB Master or Slave mode
The SMBus bi-directional SDA pin is enabled. Data input or
open drain (pull-down only) output.
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are
the user set SMBus slave address inputs.
When using an External EEPROM, a transition from high to
low starts the load from the external EEPROM
EQA[1:0] and EQB[1:0] control the level of equalization of the
A/B sides as shown in . The pins are active only when ENSMB
is de-asserted (low). Each of the 4 A/B channels have the
same level unless controlled by the SMBus control registers.
When ENSMB goes high the SMBus registers provide
independent control of each lane. The EQB[1:0] pins are
converted to SMBUS AD2, AD3 inputs. See Table 2:
Equalizer Settings.
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