CDC924_08 Datasheet, PDF (5/21 Pages) Texas Instruments – 133Mhz Clock Synthesizer/Driver

CDC924
133ĆMHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3ĆSTATE OUTPUTS
SCAS607B − NOVEMBER 1998 − REVISED JULY 2005
functional block diagram
SEL133/100 ²⁸
SEL0 ³²
SEL1 ³³
Control
Logic
3−State
48−MHz Inactive
Test
SEL133/100
XIN ⁵
XOUT ⁶
Xtal
Oscillator
48 MHz
PLL
2*REF
14.318 MHz
(2,3)
1*48MHz
48 MHz
(30)
36
CPU_STOP
SPREAD
34
Spread
Logic
37
PCI_STOP
PWR_DOWN ³⁵
/3
STOP
/4
CPU
PLL
/2
STOP
/2
/2
/3
/4
STOP
4*AGP (3V66)
66 MHz
(21,22,25,26)
4*CPU
100/133 MHz
(41,42,45,46)
2*CPU_DIV2
50/66 MHz
(49,50)
3*APIC
16.67 MHz
(53, 54, 55)
1*PCI_F
33 MHz
(8)
7*PCI
33 MHz
(9,11,12,14,
15,17,18)
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