CDC924_08 Datasheet, PDF (1/21 Pages) Texas Instruments – 133Mhz Clock Synthesizer/Driver

CDC924
133ĆMHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3ĆSTATE OUTPUTS
SCAS607B − NOVEMBER 1998 − REVISED JULY 2005
D Supports Pentium III Class Motherboards
D Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
D Includes Spread Spectrum Clocking (SSC),
0.5% Downspread for Reduced EMI
Performance
D Power Management Control Terminals
D Low Output Skew and Jitter for Clock
Distribution
D 2.5-V and 3.3-V Supplies
D Generates the Following Clocks:
− 4 CPU (2.5 V, 100/133 MHz)
− 7 PCI (3.3 V, 33.3 MHz)
− 1 PCI_F (Free Running, 3.3 V, 33.3 MHz)
− 2 CPU/2 (2.5 V, 50/66 MHz)
− 3 APIC (2.5 V, 16.67 MHz)
− 4 3V66 (3.3 V, 66 MHz)
− 2 REF (3.3 V, 14.318 MHz)
− 1 48MHz (3.3 V, 48 MHz)
D Packaged in 56-Pin SSOP Package
D Designed for Use with TI’s Direct Rambus
Clock Generators (CDCR81, CDCR82,
CDCR83)
description
The CDC924 is a clock synthesizer/driver that
generates system clocks necessary to support
Intel Pentium III systems on CPU, CPU_DIV2,
3V66, PCI, APIC, 48MHz, and REF clock signals.
DL PACKAGE
(TOP VIEW)
GND 1
REF0 2
REF1 3
V_DD3.3V 4
XIN 5
XOUT 6
GND 7
PCI_F 8
PCI1 9
V_DD3.3V 10
PCI2 11
PCI3 12
GND 13
PCI4 14
PCI5 15
V_DD3.3V 16
PCI6 17
PCI7 18
GND 19
GND 20
3V66(0) 21
3V66(1) 22
V_DD3.3V 23
GND 24
3V66(2) 25
3V66(3) 26
V_DD3.3V 27
SEL133/100 28
56 V_DD2.5V
55 APIC2
54 APIC1
53 APIC0
52 GND
51 V_DD2.5V
50 CPU_DIV2(1)
49 CPU_DIV2(0)
48 GND
47 V_DD2.5V
46 CPU3
45 CPU2
44 GND
43 V_DD2.5V
42 CPU1
41 CPU0
40 GND
39 V_DD3.3V
38 GND
37 PCI_STOP
36 CPU_STOP
35 PWR_DWN
34 SPREAD
33 SEL1
32 SEL0
31 V_DD3.3V
30 48MHz
29 GND
All output frequencies are generated from a
14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two
phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz
clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down
completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or
CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals,
the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding
setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel and Pentium III are trademarks of Intel Corporation.
Direct Rambus and Rambus are trademarks of Rambus Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2005, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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