CDC924_08 Datasheet, PDF (14/21 Pages) Texas Instruments – 133Mhz Clock Synthesizer/Driver

CDC924
133ĆMHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3ĆSTATE OUTPUTS
SCAS607B − NOVEMBER 1998 − REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
RL = 500 Ω
S1
RL = 500 Ω
VO_REF
OPEN
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VO_REF
GND
LOAD CIRCUIT for tpd and tsk
ÎÎ^tw
From Output
Under Test
Test
Point
CL
(see Note A)
LOAD CIRCUIT FOR tr and tf
3V
Input
0V
VOLTAGE WAVEFORMS
VIH_REF
VT_REF
VIL_REF
Input
VT_REF
tPLH
3V
VT_REF
0V
tPHL
Output
Enable
(high-level
enabling)
tPZL
VIH_REF
Output VT_REF
VIL_REF
tr
tw_high
tw_low
VOH
VOL
tf
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZH
VT_REF
VT_REF
VDD
0V
VT_REF
VT_REF
tPLZ
≈3 V
VOL + 0.3 V
VOL
tPHZ
VOH − 0.3 V ^VOH
≈0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. CL = 20 pF (CPUx, APICx, 48MHz, REF), CL = 30 pF (PCIx, 3V66)
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
PARAMETER
3.3-V INTERFACE
2.5-V INTERFACE
UNIT
VIH_REF High-level reference voltage
2.4
2
V
VIL_REF Low-level reference voltage
0.4
0.4
V
VT_REF Input Threshold reference voltage
1.5
1.25
V
VO_REF Off-state reference voltage
6
4.6
V
Figure 3. Load Circuit and Voltage Waveforms
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