BQ28550-R1 Datasheet, PDF (5/42 Pages) Texas Instruments – Single Cell Li-Ion Battery Gas Gauge

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Recommended Operating Conditions (continued)
T_A = 25ºC, V_BAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V_{IL_}
GPIO, SDA and SCL
Input voltage low
V_{IH_}
GPIO, SDA and SCL
Input voltage high
V_{OL_}
GPIO, SDA output
voltage low
I_OH = 3 mA (open drain)
C_I
Capacitance for each
I/O pin
SDA and SCL input capacitance
t_PUCD
Power Up
Communication Delay
V_AI2
Input voltage range
(SRP, SRN)
bq28550-R1
SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
MIN
TYP
–0.3
1.2
0
250
V_SS – 0.25
MAX
0.6
6
0.4
10
0.25
UNIT
V
V
V
pF
ms
V
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
bq28550-R1
SON
UNIT
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_{θJC(bottom)}
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter ⁽⁶⁾
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
12 PINS
186.4
90.4
110.7
96.7
90
n/a
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
6.5 Electrical Characteristics: Battery Protection
T_A = –40 to +85ºC, V_BAT =1.5 V to 5.5 V; Typical values stated, where T_A = 25ºC and V_BAT =3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V_ST
Minimum operating
voltage for 0 V charging
V_ST = V_BAT – VM
1.2
V
R_SHORT
Overcurrent release
resistance
V_BAT = 4.0 V, VM = 1 V
30
50
100
kΩ
R_DS
DS pin pull-down
resistance
V_BAT = 4.0 V
6.5
13.0
26.0
kΩ
V_OL1
COUT Low Level Output
voltage (referenced to
VM)
I_OL = 30 µA, V_BAT = 4.5 V
0.4
0.5
V
V_OH1
COUT High Level Output
voltage (referenced to
VM)
I_OH = 30 µA, V_BAT = 4.0 V
3.4
3.7
V
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