BQ24196_17 Datasheet, PDF (5/50 Pages) Texas Instruments – I2C Controlled 2.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

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bq24196
SLUSB98A – OCTOBER 2012 – REVISED DECEMBER 2014
Pin Functions (continued)
PIN
NAME NUMBER
BAT
13,14
SYS
15,16
PGND
SW
BTST
REGN
17,18
19,20
21
22
PMID
23
Thermal
Pad
–
TYPE
DESCRIPTION
P
Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected between BAT and
SYS. Connect a 10 µF closely to the BAT pin.
System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the
P minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. (Refer to Application
Information Section for inductor and capacitor selection.)
Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-
P channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A
single point connection is recommended between power PGND and the analog GND near the IC PGND pin.
O Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the
Analog drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
P
PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect
the 0.047-µF bootstrap capacitor from SW to BTST.
PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode.
P Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the
IC. REGN also serves as bias rail of TS1 and TS2 pins.
O ^{Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance,}
Analog
connect a 1-µF capacitor on VBUS to PGND, and the rest all on PMID to PGND. (Refer to Application Information Section
for details)
P
Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal
pad plane star-connecting to PGND and ground plane for high-current power converter.
7 Specifications
7.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VBUS
–2
22
V
PMID
–0.3
22
V
STAT, PG
–0.3
20
V
Voltage range (with
respect to GND)
BTST
SW
BAT, SYS (converter not switching)
–0.3
26
V
–2
20
V
–0.3
6
V
SDA, SCL, INT, OTG, ILIM, REGN, TS1, TS2, CE, PSEL
–0.3
7
V
BTST TO SW
–0.3
–7
V
PGND to GND
–0.3
–0.3
V
Output sink current
INT, STAT, PG
6
mA
Junction temperature
–40°C
150
°C
Storage temperature, T_stg
–65
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
7.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
VALUE
1000
250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
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