BQ24196_17 Datasheet, PDF (31/50 Pages) Texas Instruments – I2C Controlled 2.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

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bq24196
SLUSB98A – OCTOBER 2012 – REVISED DECEMBER 2014
8.5.1.7 Thermal Regulation Control Register REG06 (reset = 00000011, or 03)
Figure 31. REG06 Thermal Regulation Control Register Format
7
6
5
4
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
Reserved
R/W
2
Reserved
R/W
1
TREG[1]
R/W
Table 13. REG06 Thermal Regulation Control Register Description
BIT FIELD
TYPE
Bit 7 Reserved
R/W
Bit 6 Reserved
R/W
Bit 5 Reserved
R/W
Bit 4 Reserved
R/W
Bit 3 Reserved
R/W
Bit 2 Reserved
R/W
Thermal Regulation Threshold
Bit 1 TREG[1]
R/W
Bit 0 TREG[0]
R/W
RESET
0
0
0
0
0
0
1
1
DESCRIPTION
0 - Reserved
0 - Reserved
0 - Reserved
0 - Reserved
0 - Reserved
0 - Reserved
00 – 60°C, 01 – 80°C, 10 –
100°C, 11 – 120°C
NOTE
Reserved. Must write "0"
Reserved. Must write "0"
Reserved. Must write "0"
Reserved. Must write "0"
Reserved. Must write "0"
Reserved. Must write "0"
Default: 120°C (11)
0
TREG[0]
R/W
8.5.1.8 Misc Operation Control Register REG07 (reset = 01001011, or 4B)
Figure 32. REG07 Misc Operation Control Register Format
7
6
5
4
DPDM_EN TMR2X_EN
BATFET_Disable
Reserved
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
Reserved
R/W
2
Reserved
R/W
1
INT_MASK[1]
R/W
0
INT_MASK[0]
R/W
Table 14. REG07 Misc Operation Control Register Description
BIT FIELD
TYPE RESET
DESCRIPTION
NOTE
Set default input current limit from PSEL/OTG pins
Bit 7 DPDM_EN
R/W 0
0 – Not in D+/D– detection;
1 – Force D+/D– detection
Default: Not in D+/D– detection (0),
Back to 0 after detection complete
Safety Timer Setting during Input DPM and Thermal Regulation
Bit 6 TMR2X_EN
R/W 1
0 – Safety timer not slowed by 2X during
input DPM or thermal regulation,
1 – Safety timer slowed by 2X during
input DPM or thermal regulation
Default: Safety timer slowed by 2X (1)
Force BATFET Off
Bit 5 BATFET_Disable R/W 0
0 – Allow Q4 turn on, 1 – Turn off Q4 Default: Allow Q4 turn on(0)
Bit 4 Reserved
R/W 0
0 – Reserved
Bit 3 Reserved
R/W 1
1 – Reserved
Bit 2 Reserved
R/W 0
0 – Reserved
Bit 1 INT_MASK[1]
R/W 1
0 – No INT during CHRG_FAULT, 1 –
INT on CHRG_FAULT
Default: INT on CHRG_FAULT (1)
Bit 0 INT_MASK[0]
R/W 1
0 – No INT during BAT_FAULT, 1 – INT Default: INT on BAT_FAULT (1)
on BAT_FAULT
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