TMS320C6412AZDK6 Datasheet, PDF (49/163 Pages) Texas Instruments – TMS320C6412 Fixed-Point Digital Signal Processor

Device Configurations
2.3 Peripheral Selection After Device Reset
McBSP1, McBSP0, and I2C0
The C6412 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
McBSP0, McBSP1, and I2C0 peripherals. For more detailed information on the PERCFG register control bits,
see Figure 2−1 and Table 2−4.
31
24
Reserved
R-0
23
16
Reserved
R-0
15
8
Reserved
R-0
7
4
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
3
I2C0EN
R/W-0
2
MCBSP1EN
R/W-1
1
MCBSP0EN
R/W-1
0
Reserved
R-0
Figure 2−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003]
Table 2−4. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:4
Reserved
Reserved. Read-only, writes have no effect.
Inter-integrated circuit 0 (I2C0) enable bit.
3
I2C0EN
Selects whether I2C0 peripheral is enabled or disabled (default).
0 = I2C0 is disabled, and the module is powered down (default).
1 = I2C0 is enabled.
McBSP1 enable bit.
2
MCBSP1EN
0 = Reserved. Do not use.
1 = McBSP1 is enabled (default).
McBSP0 enable bit.
1
MCBSP0EN
0 = Reserved. Do not use.
1 = McBSP0 is enabled (default).
0
Reserved
Reserved. Read-only, writes have no effect.
April 2003 − Revised October 2010
SPRS219J
49