TMS320C6412AZDK6 Datasheet, PDF (102/163 Pages) Texas Instruments – TMS320C6412 Fixed-Point Digital Signal Processor

Parameter Information
3.4 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic
manner.
4 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
4.0 pF
3.5 nH
1.85 pF
Transmission Line
Z0 = 50 Ω
(see note)
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 4−1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
4.1 Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V_ref = 1.5 V
Figure 4−2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OL MAX
and V_OH MIN for output clocks, V_ILP MAX and V_IHP MIN for PCI input clocks, and V_OLP MAX and V_OHP MIN
for PCI output clocks.
V_ref = V_IH MIN (or V_OH MIN or
V_IHP MIN or V_OHP MIN)
V_ref = V_IL MAX (or V_OL MAX or
V_ILP MAX or V_OLP MAX)
Figure 4−3. Rise and Fall Transition Time Voltage Reference Levels
102 SPRS219J
April 2003 − Revised October 2010