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TMS320C6412AZDK6 Datasheet, PDF (119/163 Pages) Texas Instruments – TMS320C6412 Fixed-Point Digital Signal Processor | |||
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Synchronous DRAM Timing
WRITE
AECLKOUTx
ACEx
ABE[7:0]
AEA[22:14]
AEA[12:3]
AEA13
AED[63:0]
1
2
2
4
3
BE1
BE2
BE3
BE4
4
5
Bank
4
5
Column
4
5
9
9
10
D1
D2
D3
D4
AAOE/ASDRAS/ASOEâ
AARE/ASDCAS/ASADS/
ASREâ
AAWE/ASDWE/ASWEâ
8
8
11
11
14
14
APDTâ¡
â AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
â¡ APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write,
data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to
the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL
to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 7â2.
Figure 7â2. SDRAM Write Command for EMIFA
April 2003 â Revised October 2010
SPRS219J 119
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