TM4C1233C3PM Datasheet, PDF (483/1214 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233C3PM Microcontroller
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match
value is stored in the reading the RTCSSC field in the HIBRTCSS register and can be used in
conjunction with this register for a more precise time match.
Note:
The Hibernation module registers are on the Hibernation module clock domain and have
special timing requirements. Software should make use of the WRC bit in the HIBCTL register
to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted
write access is ignored. See “Register Access Timing” on page 470.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCM0
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCM0
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit/Field
31:0
Name
RTCM0
Type
Reset Description
RW 0xFFFF.FFFF RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
June 12, 2014
483
Texas Instruments-Production Data