TM4C1233C3PM Datasheet, PDF (137/1214 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233C3PM Microcontroller
Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184
Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188
Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C
Note: This register can only be accessed from privileged mode.
The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds
to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of
DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 (see page 138) corresponds to Interrupt
128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 97 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
INT
Type
Reset Description
RW 0x0000.0000 Interrupt Disable
Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
June 12, 2014
137
Texas Instruments-Production Data