TMS320VC5409_16 Datasheet, PDF (42/93 Pages) Texas Instruments – Digital Signal Processor

Functional Overview
3.3.5.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 3−12.
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi-Frame
Multi-Frame
Either
Either
DINM
1
1
1
1
0
0
Table 3−12. DMA Interrupts
IMOD
INTERRUPT
0
At full buffer only
1
At half buffer and full buffer
0
At block-transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
1
At end of frame and end of block (DMCTRn = 0)
X
No interrupt generated
X
No interrupt generated
3.3.5.10.1DMA Controller Synchronization Events
The internal transfers associated with each DMA channel can be synchronized to one of several events. The
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible
events and the DSYN values are shown in Table 3−13.
Table 3−13. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011b
McBSP2 receive event
0100b
McBSP2 transmit event
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b
Reserved
1000b
Reserved
1001b
Reserved
1010b
Reserved
1011b
Reserved
1100b
Reserved
1101b
Timer interrupt event
1110b
External interrupt 3
1111b
Reserved
42 _SPRS082F
April 1999 − Revised October 2008