TMS320VC5409_16 Datasheet, PDF (31/93 Pages) Texas Instruments – Digital Signal Processor

Functional Overview
3.3.1.3.1 Host Bus Holder Configuration
The 5409 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of
the address bus (A[15−0]), data bus (D[15−0]) and the HPI data bus (HD[7−0]). The bus keeper
enabling/disabling is described in Table 5.
Table 3−6. Bus Holder Control Bits
HPI16 pin
BH
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
HBH
0
1
0
1
0
1
0
1
D[15−0]
OFF
OFF
ON
ON
OFF
OFF
ON
ON
A[15−0]
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
HD[7−0]
OFF
ON
OFF
ON
ON
ON
ON
ON
The HPI bus holders are activated via the HBH bit in the Bank Switch Control Register (BSCR). The HBH bit
can control bus holder behavior for both the 8-bit and 16-bit modes. In the 8-bit mode, the HBH bit controls
the bus holders on the host data pins HD7−HD0. When HBH = 1, the host data bus holders are active. When
HBH = 0 the host data bus holders are inactive. In the 16-bit nonmultiplexed mode, the bus holders for pins
HD7−HD0 are always active; however, the HBH bit controls the host address pins A15−A0. When HBH = 1,
the host address bus holders are active. When HBH = 0, the host address bus holders are inactive.
3.3.1.4 Operation During IDLE2
The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns
on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.
The DSP CPU does not wake up from the IDLE mode during this process.
April 1999 − Revised October 2008
SPRS082F
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