TMS320VC5409_16 Datasheet, PDF (28/93 Pages) Texas Instruments – Digital Signal Processor

Functional Overview
3.2.5 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE:The hardware reset (RS) vector cannot be remapped because a hardware reset loads
the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program
space.
3.2.6 Extended Program Memory
The 5409 CPU uses a paged extended memory scheme in program space to allow access of up to 8M program
memory locations. In order to implement this scheme, the 5409 includes several features that are also present
on the 548/549 devices:
• Twenty-three address lines, instead of sixteen
• An extra memory-mapped register, the XPC register defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
• Six extra instructions for addressing extended program space. These six instructions affect the XPC.
− FB[D] pmad (23 bits) − Far branch
− FBACC[D] Accu[22:0] − Far branch to the location specified by the value in accumulator A or
accumulator B
− FCALL[D] pmad (23 bits) − Far call
− FCALA[D] Accu[22:0] − Far call to the location specified by the value in accumulator A or
accumulator B
− FRET[D] − Far return
− FRETE[D] − Far return with interrupts enabled
• In addition to these new instructions, two 54x instructions are extended to use 23 bits in the 5409:
− READA data_memory (using 23-bit accumulator address)
− WRITA data_memory (using 23-bit accumulator address)
All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access
only memory within the current page.
Program memory in the 5409 is organized into 127 pages that are each 64K in length, as shown in Figure 3−6.
28 _SPRS082F
April 1999 − Revised October 2008