DLP9000_016 Datasheet, PDF (42/59 Pages) Texas Instruments – Family of 0.9 WQXGA Type A DMDs

DLP9000
DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016
DMD Power Supply Power-Down Procedure (continued)
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EN_BIAS, EN_OFFSET, and EN_RESET are disabled by DLP controller software or PWRDNZ signal control
VBIAS, VOFFSET, and VRESET are disabled by DLP controller software
RESET_OEZ
VSS
PWRDNZ
VSS
Mirror Park Sequence
¸¸
Note 6
VCC / VCCI
¸¸
Note 3
Power Off
VCC / VCCI
VSS
VSS
VCC
VCCI
VSS
EN_BIAS
EN_OFFSET
EN_RESET _VSS
VCC / VCCI
¸¸
VCC / VCCI
¸¸
Note 3
VSS
VSS
VBIAS
VSS
VOFFSET
VSS
VSS
VRESET
LVCMOS
Inputs
VSS
VBIAS
¸¸
VBIAS
Note 1
¨9 < Specification
VOFFSET
¸¸
Note 1
¨9 < Specification
VOFFSET
VBIAS < Specification
Note 4
VSS
VOFFSET < Specification
Note 5
Refer to specifications listed in Recommended Operating Conditions.
Waveforms are not to scale. Details are omitted for clarity.
Note 4
VSS
VRESET < Specification
Note 4
VSS
VRESET
¸¸
VRESET
VRESET > Specification
VCC
¸¸
VSS
Note 2
LVDS
Inputs
VSS
¸¸
Note 2
VSS
Figure 19. DMD Power Supply Sequencing Requirements
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