DLP9000_016 Datasheet, PDF (11/59 Pages) Texas Instruments – Family of 0.9 WQXGA Type A DMDs

www.ti.com
DLP9000
DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) ⁽¹⁾
SUPPLY VOLTAGES
VCC
VCCI
VOFFSET
VBIAS
VRESET
| VCC – VCCI |
| VBIAS – VOFFSET |
INPUT VOLTAGES
| V_ID |
I_ID
CLOCKS
ƒ_clock
ENVIRONMENTAL
T_ARRAY
T_WINDOW
|T_DELTA|
RH
Supply voltage for LVCMOS core logic ⁽²⁾
Supply voltage for LVDS receivers ⁽²⁾
Supply voltage for HVCMOS and micromirror electrode ^{(2) (3)}
Supply voltage for micromirror electrode ⁽²⁾
Supply voltage for micromirror electrode ⁽²⁾
Supply voltage delta (absolute value) ⁽⁴⁾
Supply voltage delta (absolute value) ⁽⁵⁾
Input voltage for all other LVCMOS input pins ⁽²⁾
Input voltage for all other LVDS input pins ^{(2) (6)}
Input differential voltage (absolute value) ⁽⁷⁾
Input differential current ⁽⁷⁾
DLP9000
DLP9000X
Clock frequency for LVDS interface, DCLK_A
Clock frequency for LVDS interface, DCLK_B
Clock frequency for LVDS interface, DCLK_C
Clock frequency for LVDS interface, DCLK_D
Clock frequency for LVDS interface, DCLK_A
Clock frequency for LVDS interface, DCLK_B
Clock frequency for LVDS interface, DCLK_C
Clock frequency for LVDS interface, DCLK_D
Array temperature: operational ^{(8) (9)}
Array temperature: non–operational ⁽⁹⁾
Window temperature: operational
Window temperature: non–operational
Absolute termperature delta between the window test points and the
ceramic test point TP1⁽¹⁰⁾
Relative Humidity, operating and non–operating
MIN
MAX
UNIT
–0.5
4
V
–0.5
4
V
–0.5
9
V
–0.5
17
V
–11
0.5
V
0.3
V
8.75
V
–0.5
VCC + 0.3
V
–0.5
VCCI + 0.3
V
700
mV
7
mA
440
440
440
440
MHz
500
500
500
500
0
90
ºC
-40
90
0
70
ºC
-40
90
10
ºC
95%
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.
(2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected.
(3) VOFFSET supply transients must fall within specified voltages.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Requirements for additional information.
(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential
temperature, or illumination power density may affect device reliability.
(9) The highest temperature of the active array as calculated by the Micromirror Array Temperature Calculation using ceramic test point 1
(TP1) in Figure 15.
(10) Temperature delta is the highest difference between the ceramic test point TP1 and window test points TP2 and TP3 in Figure 15.
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: DLP9000
Submit Documentation Feedback
11