ADS5400 Datasheet, PDF (42/55 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400
SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016
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Typical Application (continued)
In Equation 6, the parameters of the equation may be seen to be in terms of signal amplitude in the numerator
and amplifier noise in the denominator, or SNR. For the numerator, use the full scale voltage specification of the
ADS5400, or 2 V peal to peak differential. Because Equation 6 requires the signal voltage to be in rms, convert 2
V_PP to 0.706 V rms.
The noise specification for the LMH3401 is listed as 3.4 nV/√Hz, therefore, use this value to integrate the noise
component from DC out to the filter cutoff, using the equivalent brick wall filter of 400 MHz × 1.57, or 628 MHz.
3.4 nV/√Hz integrated over 628 MHz yields 85204 nV, or 85.204 µV.
Using 0.706 V rms for V_O and 85.204 µV for E_FILTEROUT, (see Equation 6) the SNR of the amplifier and filter as
given by Equation 6 is approximately 78.4 dB.
Taking the SNR of the ADC as 58.8 dB from Figure 39, and SNR of the amplifier and filter as 78.4 dB,
Equation 5 predicts the system SNR to be 58.75 dB. In other words, the SNR of the ADC and the SNR of the
front end combine as the square root of the sum of squares, and because the SNR of the amplifier front end is
much greater than the SNR of the ADC in this example, the SNR of the ADC dominates Equation 5 and the
system SNR is almost the same as the SNR of the ADC. The assumed design requirement is 58 dB, and after a
clocking solution was selected and an amplifier or filter solution was selected, the predicted SNR is 58.75 dBFS.
8.2.3 Application Curve
Figure 39 shows the SNR of the ADC as a function of clock jitter and input frequency for the ADS5400. This plot
of curves take into account the aperture jitter of the ADC, the number of bits of resolution, and the thermal noise
estimation so that Figure 39 may be used to predict SNR for a given input frequency and external clock jitter.
Figure 39 then may be used to set the jitter requirement for the clocking solution for a given input bandwidth and
given design goal for SNR.
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10
35 fs
50 fs
100 fs
150 fs
200 fs
100
Fin (MHz)
1000
3000
D001
Figure 39. SNR vs Input Frequency and External Clock Jitter
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