ADS5400 Datasheet, PDF (14/55 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400
SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016
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Sample N and RESET
pulse captured here
CLKINP
t_RSU
RESETP
N+1
t_RH
N, N+1
output
CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2 )
tPD-CLKDIV2
CLKOUTAP
CLKOUTBP
Phase 0: CLKOUT in desired
state after power up
Phase 1: misaligned by 1
clock after power up
DATA BUS B
SYNCOUTB
(OVRB pins)
DATA BUS A
tPD-BDATA
Latency of N and SYNCOUTB are matched to 8.5 CLKIN cycles
The phase of data shown prior to reset matches CLKOUT in phase 0
If SYNC mode is enabled,
the OVRB pins become SYNCOUTB pins
The phase of data shown prior to reset matches CLKOUT in phase 0
t_su
t_h
N
N+2
Sync
N+1
N+3
Latency of N+1 is 7.5 CLKIN cycles
tPD-ADATA
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, to keep the CLKOUT
phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present
when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse,
which behaves as a data bit.
Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2
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