LMK04828-EP Datasheet, PDF (41/102 Pages) Texas Instruments – Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

www.ti.com
LMK04828-EP
SNAS703 – APRIL 2017
Register Maps (continued)
ADDRESS
[11:0]
0x15E
0x15F
0x160
0x161
0x162
0x163
0x164
0x165
0x166
0x167
0x168
0x169
0x16A
0x16B
0x16C
0x16D
0x16E
0x171
0x172
0x173
0x174
0x17C
0x17D
0x182
0x183
0x184
0x185
0x188
0x1FFD
0x1FFE
0x1FFF
Table 9. LMK04828-EP Register Map (continued)
7
6
5
0
0
PLL1_LD_MUX
0
0
0
PLL2_P
0
0
0
0
0
0
0
PLL2_WND_SIZE
0
SYSREF_REQ_
EN
0
0
PLL2_LF_C4
PLL2_LD_MUX
1
0
1
0
0
0
0
PLL2_PRE_PD PLL2_PD
0
0
0
0
0
0
0
RB_DAC_VALUE[9:8]
0
0
0
0
RB_CLKin2_
SEL
0
DATA
4
3
PLL1_R_DLY
0
PLL2_R[7:0]
OSCin_FREQ
0
0
PLL2_N_CAL[15:8]
PLL2_N_CAL[7:0]
0
0
PLL2_N[15:8]
PLL2_N[7:0]
PLL2_CP_GAIN
2
1
0
PLL1_N_DLY
PLL1_LD_TYPE
PLL2_R[11:8]
PLL2
_XTAL_EN
PLL2
_REF_2X_EN
0
PLL2_N_CAL[17:16]
PLL2_FCAL
_DIS
PLL2_N[17:16]
PLL2
_CP_POL
PLL
2_CP_TRI
1
PLL2_DLD_CNT[15:8]
PLL2_DLD_CNT[7:0]
PLL2_LF_R4
0
1
0
0
0
0
OPT_REG_1
OPT_REG_2
0
0
0
0
RB_CLKin1_
SEL
RB_CLKin0_
SEL
RB_DAC_VALUE[7:0]
RB_
HOLDOVER
X
SPI_LOCK[23:16]
SPI_LOCK[15:8]
SPI_LOCK[7:0]
PLL2_LF_R3
PLL2_LF_C3
PLL2_LD_TYPE
0
1
0
0
1
0
0
0
0
VCO1_DIV
RB_PLL1_
LD_LOST
RB_PLL2_
LD_LOST
X
RB_PLL1_LD
RB_PLL2_LD
RB_CLKin1_
LOS
CLR_PLL1_
LD_LOST
CLR_PLL2_
LD_LOST
RB_CLKin0_
LOS
X
X
X
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK04828-EP
Submit Documentation Feedback
41