LMK04828-EP Datasheet, PDF (35/102 Pages) Texas Instruments – Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

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LMK04828-EP
SNAS703 – APRIL 2017
9.4.2 0-DELAY Dual PLL
Figure 13 illustrates the use case of cascaded 0-delay dual loop mode. This configuration differs from dual loop
mode Figure 12 in that the feedback for PLL2 is driven by a clock output instead of the VCO output. Figure 14
illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in DUAL
PLL except that the feedback to the first PLL is driven by a clock output. This causes the clock outputs to have
deterministic phase relationship with the clock input. Since all the clock outputs can be synchronized together, all
the clock outputs can share the same deterministic phase relationship with the clock input signal. The feedback
to PLL1 can be connected internally as shown using CLKout6, CLKout8, SYSREF, or externally using FBCLKin
(CLKin1).
It is also possible to use an external VCO in place of the internal VCO of PLL2, but one less CLKin is available
as a reference and external 0-delay feedback is not available.
CLKinX
CLKinX*
Up to 3
inputs
PLL1
R
Phase
Detector
PLL1
N
External VCXO
or Tunable
Crystal
External
Loop Filter
Input
Buffer
LMK0482x
Internal or external loopback, user programmable
PLL2
Up to 1 OSCout
OSCout
OSCout*
External
Loop Filter
CPout2
R
Divider
Phase
Partially
Digital Delay
Detector Integrated
Analog Delay
PLL2
Loop Filter
N
Dual
7 blocks
Internal
VCOs
SYSREF
Analog Delay
Digital Delay
1 Global SYSREF Divider
SDCLKoutY
SDCLKoutY*
7 SYSREF
or Device
Clocks
DCLKoutX
DCLKoutX*
7 Device
Clocks
Copyright © 2017, Texas Instruments Incorporated
Figure 13. Simplified Functional Block Diagram for Cascaded 0-delay Dual Loop Mode
FIELD
PLL1_NCLK_MUX
PLL2_NCLK_MUX
FB_MUX_EN
FB_MUX
OSCin_PD
CLKin0_OUT_MUX
CLKin1_OUT_MUX
VCO_MUX
Table 7. Cascaded 0-delay Dual Loop Mode Register Configuration
REGISTER
ADDRESS
0x13F
0x13F
0x13F
0x13F
0x140
0x147
0x147
0x138
FUNCTION
Selects the input to the PLL1 N divider.
Selects the input to the PLL2 N divider
Enables the Feedback Mux.
Selects the output of the Feedback Mux.
Powers down the OSCin port.
Selects where the output of CLKin0 is directed.
Selects where the output of CLKin1 is directed.
Selects the VCO 0, 1, or an external VCO
VALUE
0
1
1
0, 1, or 2
0
0
0 or 2
0 or 1
SELECTED VALUE
OSCin
Feedback Mux
Feedback Mux Enabled
Select between DCLKout6,
DCLKout8, SYSREF
Powered up
PLL1
Fin or PLL1
VCO 0 or VCO 1
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